Plasma processes are commonly used to produce inter-metal dielectric (IMD) layers to reduce the RC delay in the interconnects that connect metal layers in integrated circuits. For example, a high-density plasma oxide such as a fluorine doped high-density plasma (FHDP) oxide is commonly used as an IMD layer to reduce the RC delay in sub-0.18 micron aluminum interconnects. An example of this is illustrated in FIG. 1, wherein an FHDP oxide is provided as an IMD layer 18 between a metal layer 17 and an upper metal layer (not explicitly shown). As mentioned above, the IMD layer 18 can reduce the RC delay in interconnects (not explicitly shown) that connect the metal layer 17 to upper metal layers. Also in FIG. 1, a metal interconnect 16 connects the metal layer 17 to a gate 13 of a metal oxide semiconductor (MOS) transistor whose gate oxide is shown at 12 and whose channel extends through the semiconductor substrate illustrated generally at 11. The gate 13 is typically polysilicon. A pre-metal dielectric (PMD) stack 15 formed from phosphorus-doped tetraethyl orthosilicate (TEOS) deposited by chemical vapor deposition (CVD) is interposed between the gate 13 and the metal layer 17. An etch stop layer 14 (typically a semiconductive material) is used in a patterning and etching process associated with the positioning of the metal interconnect (gate contact) 16.
The plasma process used to deposit the IMD dielectric 18, for example a high-density plasma process such as the aforementioned FHDP process, is known to damage the gate oxide 12. This damage is commonly referred to as plasma process induced damage or PPID. On the other hand, high-density plasma process deposition has several advantageous features which are well known to workers in the art.
It is therefore desirable to provide for a reduction in the gate oxide damage caused by plasma process deposition of IMD layers.